Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card

ABSTRACT

A semiconductor memory card is provided that performs high-speed data communication without any collision between input data and output data being caused on the data line. The semiconductor memory card of the present invention includes: a data storing part; a control part writing and reading data into and from the data storing part; an interface circuit; and a plurality of input and output terminals. In the input and output terminals, roles of a data input terminal pair and a data output terminal pair are each allotted to a different terminal pair so that no terminal pair acts as both the data input terminal pair and the data output terminal pair, and a clock input terminal and a clock output terminal are included. The interface circuit receives an input clock from the clock input terminal, receives a complementary input data pair synchronized with the input clock from the data input terminal pair, outputs a complementary output data pair from the data output terminal pair, and outputs an output clock synchronized with the complementary output data pair from the clock output terminal.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor memory card, amethod of controlling the semiconductor memory card and an interfaceapparatus for semiconductor memory card.

[0002] Semiconductor memory cards with a minimized number of terminalsand interface standards for the semiconductor memory cards have beenproposed for size reduction of semiconductor memory cards and hostapparatuses of the semiconductor memory cards. A prior art semiconductormemory card will be described with reference to FIG. 8 and FIG. 9. FIG.8 is a block diagram of the already proposed prior art semiconductormemory card (including an internal block diagram of an interface circuitof the semiconductor memory card). In FIG. 8, the semiconductor memorycard 801 comprises: a data storing part 802 including a flash memory, aDRAM, an SRAM and the like for storing data; a control circuit 803writing and reading data into and from the data storing part 802; aninterface circuit 804 performing data input and output with the hostapparatus; and a connection terminal 805.

[0003] As an example of the semiconductor memory card 801, one prior artsemiconductor memory card has been proposed that supports two kinds ofinterface standards as shown in FIG. 9 in order that the semiconductormemory card is adaptable to diversification of interface specificationsof host apparatuses. FIG. 9 shows the attributes and the functionsallotted to nine terminals of the prior art semiconductor memory cardsupporting the two kinds of interface standards when the semiconductormemory card operates according to the two interface standards (a firstoperation mode and a second operation mode). A first terminal structure(first operation mode) and a second terminal structure (second operationmode) are as shown in FIG. 9. Of the structures based on thespecifications of the two kinds of operation modes shown in FIG. 9, thestructure based on the interface specification of the second operationmode is shown in FIG. 8.

[0004] In the structure of FIG. 8, the attribute of a terminal 1 of theconnection terminal 805 is “input”, and the function allotted thereto is“chip select input”. The terminal 1 inputs a command signal CS to thecontrol circuit 806 through a buffer 810. The attribute of a terminal 2is “input”, and the function allotted thereto is “data input”. Theterminal 2 inputs input data DI to the control circuit 806 through adata input buffer 807. The attribute of a terminal 5 is “input”, and thefunction allotted thereto is “clock input”. The terminal 5 inputs aclock signal CLK to the control circuit 806 through a buffer 809. Theattribute of a terminal 7 is “output”, and the function allotted theretois “data output”. Output data DO is output from the terminal 7 through adata output buffer 808. The attributes of terminals 3, 4 and 6 are“power supply”, and the functions allotted to the terminals 3, 4 and 6are “connection to the ground potential”, “connection to the powersupply potential” and “connection to the ground potential”,respectively. The attributes of terminals 8 and 9 are “high impedance”,and the terminals 8 and 9 are unused.

[0005] In the prior art semiconductor memory card 801, the functionsaccording to the second operation mode are allotted to the terminals asdescribed above. The semiconductor memory card 801 in the secondoperation mode performs data writing and reading with a host apparatusof the interface specification of the second operation mode. FIG. 8 doesnot show the connection structure of the interface circuit 804 in thefirst operation mode. In the first operation mode, the interface circuit804 of the semiconductor memory card is structured based on thespecification shown in FIG. 9. The semiconductor memory card in thefirst operation mode performs data writing and reading with a hostapparatus of the interface specification of the first operation mode.

[0006] In the prior art semiconductor memory card, when data istransmitted, in the first operation mode, both “input” and “output” areallotted to one terminal (line), so that when data is transmitted in twodirections at the same time, data collision occurs on one line. For thisreason, high-speed data communication control of executing datatransmission in two directions at the same time cannot be performed. Theprior art semiconductor memory card uses the input clock input to theterminal 5 as it is as the clock for data output. Therefore, when theclock frequency is high, a timing shift between the data and the clockis caused on the receiving side (the host apparatus connected to thesemiconductor memory card). Moreover, in the second operation mode,because of the presence of the unused terminals (lines), it cannot besaid that terminals are efficiently used.

[0007] The present invention is made with an object of providing asemiconductor memory card enabling high-speed data communication controland being capable of eliminating a timing shift between the output dataand the output clock on the receiving side (the host apparatus connectedto the semiconductor memory card), a method of controlling thesemiconductor memory card and an interface apparatus for semiconductormemory card.

BRIEF SUMMARY OF THE INVENTION

[0008] To achieve this object, a semiconductor memory card according toan aspect of the invention comprises: a data storing part; a writing andreading control part writing and reading data into and from the datastoring part; an interface circuit; and a plurality of input and outputterminals. In the input and output terminals, roles of a data inputterminal pair and a data output terminal pair are each allotted to adifferent terminal pair so that no terminal pair acts as both the datainput terminal pair and the data output terminal pair, and a clock inputterminal and a clock output terminal are included. The interface circuitreceives an input clock from the clock input terminal, receives acomplementary input data pair synchronized with the input clock from thedata input terminal pair, outputs a complementary output data pair fromthe data output terminal pair, and outputs an output clock synchronizedwith the complementary output data pair from the clock output terminal.

[0009] According to the present invention, input data and output datanever collide with each other on the data line, so that high-speed datacommunication control is enabled. Moreover, since the transmission datais differential data (complementary data pair), the S/N ratio of thetransmission data is improved, so that high-speed sensing is enabled onthe receiving side. At the same time, by the data amplitude being smallon the output side, the clock frequency can be increased without theslew rate in the output stage being changed. According to the presentinvention, an input clock and an output clock having different phasesare synchronized with input data and output data, respectively. Thepresent invention realizes a semiconductor memory card in which a timingshift between the clock and the data due to a delay on the transmissionline is eliminated.

[0010] The semiconductor memory card according to another aspect of theinvention performs data input and output with a host apparatus. Theinterface circuit receives an input clock output by the host apparatusand input data synchronized with the input clock. The interface circuitgenerates the output clock having a phase different from a phase of theinput clock and being synchronized with the complementary output datapair by adjusting a timing of the input clock, outputs the output clockfrom the clock output terminal, and outputs the complementary outputdata pair from the data output terminal pair.

[0011] The present invention realizes a semiconductor memory cardrequiring no clock generating part.

[0012] A semiconductor memory card according to another aspect of theinvention comprises: an interface circuit setting an attribute and afunction of each of a plurality of input and output terminals andperforming internal setting in accordance with an operation modeselected and set from among a plurality of operation modes including ahigh-speed operation mode; and the plurality of input and outputterminals. In the high-speed operation mode, the plurality of input andoutput terminals comprise: a clock input terminal to which an inputclock is input; a clock output terminal from which an output clock isoutput; a data input terminal pair to which a complementary input datapair synchronized with the input clock is input; and a data outputterminal pair from which a complementary output data pair is output. Theinterface circuit comprises the following as elements operating at leastin the high-speed operation mode: a switch capable of being switched inaccordance with the high-speed operation mode; a differential inputbuffer receiving the complementary input data pair, sensing a differencebetween the complementary input data pair by the input clock, andlatching the difference; a differential output buffer receiving outputdata and outputting the output data by the input clock as thecomplementary output data pair; and a timing adjusting circuit receivingthe input clock, adjusting a timing of the input clock with thecomplementary output data pair, and outputting, as the output clock, theinput clock timing-adjusted so as to be synchronized with thecomplementary output data pair.

[0013] The present invention realizes a semiconductor memory cardadaptable to the interface specifications of a plurality of operationmodes, and particularly, are adaptable to the high-speed operation modewithout the number of connection terminals being increased.

[0014] In the semiconductor memory card according to still anotheraspect of the invention, the interface circuit has output impedanceadjusting circuit(s) each of between the data output terminal pair andthe differential output buffer and between the output clock terminal andthe timing adjusting circuit.

[0015] The present invention realizes a semiconductor memory card inwhich impedance matching with the signal line is obtained.

[0016] In the semiconductor memory card according to still anotheraspect of the invention, the interface circuit further comprises a bandpass filter receiving the input clock and allowing only a predeterminedfrequency band component to pass through the band pass filter. Thepresent invention realizes a semiconductor memory card in which a clockwith a small amount of ringing component and a high S/N ratio isextracted by capturing only the predetermined frequency band component.

[0017] In the semiconductor memory card according to still anotheraspect of the invention, a passband frequency of the band pass filter isselectable.

[0018] The present invention realizes a semiconductor memory card inwhich a timing shift due to a reflected wave is prevented by capturing aclock of a predetermined frequency band with reliability and changingthe frequency setting.

[0019] A semiconductor memory card controlling method according to stillanother aspect of the invention is a method of controlling, in ahigh-speed operation mode, a semiconductor memory card having aplurality of input and output terminals and performing data input andoutput with a host apparatus in a plurality of operation modes includinga normal operation mode and the high-speed operation mode. The methodcomprises the steps of: setting the high-speed operation mode inresponse to a setting command of the high-speed operation mode from thehost apparatus; switching an operation of the semiconductor memory cardso that data transmission and reception can be performed in thehigh-speed operation mode; allotting roles of a data input terminalpair, a data output terminal pair, a clock input terminal and a clockoutput terminal separately to the input and output terminals so thatnone of the input and output terminals has a plurality of roles;inputting an input clock from the clock input terminal and inputting acomplementary input data pair synchronized with the input clock from thedata input terminal pair; generating an output clock having a phasedifferent from a phase of the input clock, by adjusting a timing of theinput clock; and outputting the output clock from the clock outputterminal and outputting a complementary output data pair synchronizedwith the output clock from the data output terminal pair.

[0020] A slave apparatus according to still another aspect of theinvention is a slave apparatus performing synchronous data transmissionaccording to a master/slave method with a host apparatus as a master anda slave apparatus as a slave. The slave apparatus comprises: an inputpart inputting a clock and data output by the host apparatus insynchronism with each other; and an output part outputting to the hostapparatus the clock being input or a clock obtained by timing-adjustingthe clock, and data in synchronism with each other.

[0021] In the slave apparatus according to still another aspect of theinvention, the slave apparatus is a semiconductor memory card.

[0022] The present invention realizes a slave apparatus (e.g.semiconductor memory card) performing high-data-rate and stable datatransmission according to a master/slave method under a condition wherethe master apparatus (host apparatus) maintains a function toappropriately control the entire communication.

[0023] An interface apparatus for a semiconductor memory card accordingto still another aspect of the invention is an interface apparatus for asemiconductor memory card comprising: an interface circuit setting anattribute and a function of each of a plurality of input and outputterminals and performing internal setting in accordance with anoperation mode selected and set from among a plurality of operationmodes including a high-speed operation mode; and the plurality of inputand output terminals. In the high-speed operation mode, the plurality ofinput and output terminals comprise: a clock input terminal to which aninput clock is input; a clock output terminal from which an output clockis output; a data input terminal pair to which a complementary inputdata pair synchronized with the input clock is input; and a data outputterminal pair from which a complementary output data pair is output. Theinterface circuit comprises the following as elements operating at leastin the high-speed operation mode: a switch capable of being switched inaccordance with the high-speed operation mode; a differential inputbuffer receiving the complementary input data pair, sensing a differencebetween the complementary input data pair by the input clock, andlatching the difference; a differential output buffer receiving outputdata and outputting the output data by the input clock as thecomplementary output data pair; and a timing adjusting circuit receivingthe input clock, adjusting a timing of the input clock with thecomplementary output data pair, and outputting, as the output clock, theinput clock timing-adjusted so as to be synchronized with thecomplementary output data pair.

[0024] The present invention realizes an interface apparatus for asemiconductor memory card adaptable to the interface specifications of aplurality of operation modes, and particularly, are adaptable to thehigh-speed operation mode without the number of connection terminalsbeing increased.

[0025] The novel features of the invention are set forth withparticularity in the appended claims. The invention, both as to theconstruction and contents, together with further objects and featureswill be better understood and appreciated from the following detaileddescription taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a block diagram of a semiconductor memory card accordingto a first embodiment of the present invention (including an internalblock diagram of an interface circuit of the semiconductor memory card);

[0027]FIG. 2 is a general block diagram detailing the power supply lineof the semiconductor memory card according to the first embodiment ofthe present invention;

[0028]FIG. 3 is a block diagram showing a connection relationshipbetween the semiconductor memory card and a host apparatus according tothe first embodiment of the present invention;

[0029]FIG. 4 is a view showing the waveforms of input and output signalsof the semiconductor memory card 1 according to the first embodiment ofthe present invention, and the timing among the signals;

[0030]FIG. 5 is an explanatory view showing the attributes and thefunctions of the terminals of a semiconductor memory card according to asecond embodiment of the present invention in each operation mode;

[0031]FIG. 6 is a concrete circuit diagram of the semiconductor memorycard according to the second embodiment of the present invention;

[0032]FIG. 7 is a flowchart of selection of the operation mode of thesemiconductor memory card according to the second embodiment of thepresent invention;

[0033]FIG. 8 is a block diagram of the prior art semiconductor memorycard (including an internal block diagram of the interface circuit ofthe semiconductor memory card);

[0034]FIG. 9 is an explanatory view showing the attributes and thefunctions of the terminals of the prior art semiconductor memory card ineach operation mode;

[0035]FIG. 10 is a block diagram showing the structure of a timingadjusting circuit 10 according to the first embodiment of the presentinvention;

[0036]FIG. 11 is a block diagram showing the structure of a timingadjusting circuit according to another embodiment of the presentinvention; and

[0037]FIG. 12 is a concrete circuit diagram of a host apparatus 615according to the second embodiment of the present invention.

[0038]FIG. 13 is a block diagram of a system comprising: a hostapparatus 615, an interface apparatus 1301 according to the thirdembodiment of the present embodiment and a semiconductor memory card1302 according to the third embodiment of the present embodiment.

[0039] It will be recognized that some or all of the Figures areschematic representations for purposes of illustration and do notnecessarily depict the actual relative sizes or locations of theelements shown.

DETAILED DESCRIPTION OF THE INVENTION

[0040] Hereinafter, embodiments of the semiconductor memory card, amethod of controlling the semiconductor memory card and an interfaceapparatus for semiconductor memory card according to the presentinvention will be described in detail with reference to the drawings.

[0041] <<Embodiment 1>>

[0042] A semiconductor memory card 1 and a host apparatus 15 accordingto a first embodiment of the present invention will be described withreference to FIG. 1 to FIG. 4, FIG. 10 and FIG. 11. FIG. 1 is a blockdiagram of the semiconductor memory card 1 according to the firstembodiment of the present invention (including an internal block diagramof an interface circuit of the semiconductor memory card). FIG. 2 is ageneral block diagram detailing the power supply line of thesemiconductor memory card 1 according to the first embodiment. FIG. 3 isa block diagram showing the connection relationship between thesemiconductor memory card 1 and the host apparatus 15 according to thefirst embodiment. FIG. 4 is a timing chart showing the waveforms ofsignals of the semiconductor memory card 1 according to the firstembodiment.

[0043] In FIG. 1 to FIG. 4, the semiconductor memory card 1 comprises: adata storing part 2 including a flash memory, a DRAM and/or an SRAM forstoring data; a writing and reading control circuit 3 writing andreading data into and from the data storing part 2; an interface circuit4 performing data input and output with the host apparatus 15; and aconnection terminal 5. The data storing part 2 typically includes anonvolatile memory such as a flash memory. The interface circuit 4comprises: an interface control circuit 4 a performing input and outputcontrol on the writing and reading control circuit 3; and an input andoutput circuit described later and disposed between the interfacecontrol circuit 4 a and the connection terminal 5.

[0044] The connection terminal 5 comprises nine terminals 1 to 9. In thefirst embodiment, to the terminal 1, an input clock CLKIN is input, tothe terminal 2, a non-inverted signal DI+ (one of a complementary datapair) of differential input data, to the terminal 3, a first groundpotential VSS is connected, to the terminal 4, a power supply potentialVDD is connected, from the terminal 5, an output clock CLKOUT is output,to the terminal 6, a first ground potential VSS2 is connected, from theterminal 7, a non-inverted signal DO+ (one of a complementary outputdata pair) of differential output data is output, from the terminal 8,an inverted output DO− (the other of the complementary output data pair)of the differential output data is output, and to the terminal 9, aninverted signal DI− of the differential input data is input. Theterminals 2 and 9 constitute a data input terminal pair to which thecomplementary input data pair is input. The terminals 7 and 8 constitutea data output terminal pair from which the complementary output datapair is output.

[0045] The connection condition of the terminals in the entiresemiconductor memory card 1 is shown in FIG. 2. As shown in FIG. 2, theterminals 4, 3 and 6 serving as power supply terminals are connected tothe circuit blocks of the data storing part 2, the writing and readingcontrol circuit 3 and the interface circuit 4. The other terminals areconnected only to the interface circuit 4.

[0046] The input clock CLKIN input to the terminal 1 is input as a clockCLK to the interface control circuit 4 a and differential input buffers8 and 9 through a band pass filter 6 and an input buffer 7. The bandpass filter 6 allows only frequencies in the neighborhood of thefundamental frequency of the input clock CLKIN to pass therethrough. Theband pass filter 6 attenuates the ringing component of the input clockCLKIN and improves the S/N ratio of the input clock having passedthrough the band pass filter. When the frequency of the input clockCLKIN is changed, the passband of the band pass filter 6 may be changedin accordance with a selection signal output by the interface controlcircuit 4 a.

[0047] The differential input data DI+ and DI− input to the terminals 2and 9 are input to the differential input buffer 8. The differentialinput buffer 8 senses, latches and outputs the input data DI which isthe difference between the differential input data DI+ and DI− on therising edge of the clock CLK output by the input buffer 7. The interfacecontrol circuit 4 a latches and receives the input data DI on thefalling edge (or the rising edge) of the clock CLK.

[0048] The interface circuit 4 a outputs the output data DO on thefalling edge (or the rising edge) of the clock CLK. The differentialoutput buffer 9 receives the output data DO, latches the output data DOon the rising edge of the clock CLK, and outputs the differential outputdata DO+ and DO−. The differential output data DO+ and DO− are outputfrom the terminals 7 and 8 through output impedance adjusting circuits13 and 14, respectively.

[0049] A timing adjusting circuit 10 receives the clock CLK, delays theclock CLK (adjusts the timing of the clock CLK) so that the relativephases of the data and the clock are optimum on the receiving side tothereby synchronize the clock CLK with the complementary output datapair, and outputs a timing-adjusted clock signal Delayed CLK. Thetiming-adjusted clock signal Delayed CLK is output, as an output clockCLKOUT, from the terminal 5 through an output buffer 11 and an outputimpedance adjusting circuit 12.

[0050] The clock CLK input through the band pass filter 6 and the inputbuffer 7 is supplied to the differential input buffer 8. Thedifferential input buffer 8 senses the differential input data DI+ andDO− and at the same time, lathes the input data DI which is thedifference therebetween. The clock CLK is supplied to the differentialoutput buffer 9. The differential output buffer 9 latches, on the risingedge of the clock CLK, the output data DO output from the interfacecontrol circuit 4 a, and outputs the differential output data DO+ andDO− (the complementary output data pair of the output data DO). Theoutput impedance adjusting circuits 12, 13 and 14 are provided forobtaining matching with the signal lines. The output impedance adjustingcircuits 12, 13 and 14 are, for example, low-impedance resistors or beadfilters. The output impedance adjusting circuits 12, 13 and 14 suppressthe ringing components of the output clock CLKOUT and the differentialoutput data DO+ and DO−.

[0051]FIG. 10 is a block diagram showing the structure of the timingadjusting circuit 10 according to the first embodiment. In FIG. 10, aphase comparator 1011, a voltage controlled oscillator 1012 and aquarter frequency divider 1013 constitute a phase-locked loop 1001. Thephase-locked loop 1001 outputs a signal CLK (fCLK,0) phase-synchronizedwith the clock CLK (frequency fCLK) and having the same frequency fCLK,and a signal 4CLK (4fCLK) having a frequency 4fCLK four times thefrequency fCLK. D latch circuits 1002 to 1004 receive the signal 4CLK(4fCLK) as a latch clock. The D latch circuits 1002 to 1004 successivelydelay the signal CLK (fCLK,0), and output a signal CLK (fCLK,π/2)phase-delayed by π/2 from the clock CLK, a signal CLK (fCLK,π)phase-delayed by π from the clock CLK and a signal CLK (fCLK,3π/2)phase-delayed by 3π/2 from the clock CLK, respectively. A switch 1005selects one of the signal CLK (fCLK,0), the signal CLK (fCLK,π/2), thesignal CLK (fCLK,π) and the signal CLK (fCLK,3π/2) in accordance with aselection signal output by a control circuit 5 a, and outputs theselected signal as the signal Delayed CLK. The control circuit 5 aoutputs, in accordance with the clock frequency, the selection signal tosynchronize the clock and the data with each other so that the relativephases of the data and the clock are optimum on the receiving side.

[0052]FIG. 11 is a block diagram showing the structure of the timingadjusting circuit 10 according to another embodiment. In FIG. 11,reference numerals 1101 to 1110 represent buffers. The clock CLK istransmitted on four paths. A different number of buffers are disposed oneach line. The larger the number of buffers is, the more the clock CLKis delayed. A switch 1111 selects one of the clocks CLK having passedthrough the four paths in accordance with the selection signal output bythe control circuit 5 a, and outputs the selected signal as the signalDelayed CLK.

[0053] When the frequency of the clock CLK is constant, the switchingcircuits (the switches 1005, 1111, etc.) of FIG. 10 and FIG. 11 may beomitted.

[0054] As described above, by separating the transmission line for inputdata and the transmission line for output data, when input data andoutput data are transmitted or received at the same time, the input dataand the output data never collide with each other. High-speedcommunication control of transmitting or receiving input data and outputdata at the same time is enabled. Moreover, by transmitting thedifferential data, the SIN ratio of the data is improved on the inputside, so that high-speed sensing of the data is enabled. At the sametime, by the data amplitude being small on the output side, the clockfrequency can be increased without the slew rate in the output stagebeing improved. The input circuit and the output circuit sense and latchdata with clocks of different phases generated from one clock. Thisenables elimination of the timing shift between the data and the clockdue to a delay on the transmission line. According to the presentinvention, the data and the clock are synchronized with each other in anoptimum phase at the input circuit and the output circuit.

[0055] Next, a case where the semiconductor memory card structured asdescribed above is connected to the host apparatus will be describedwith reference to FIG. 3.

[0056]FIG. 3 shows a condition where the semiconductor memory card 1 isconnected by being inserted in a card connector of the host apparatus15. FIG. 3 shows the connection condition of only the signal lines. Thehost apparatus 15 and the semiconductor memory card 1 performsynchronous data transmission according to a master/slave method withthe host apparatus 15 as the master and the semiconductor memory card 1as the slave. The host apparatus 15 comprises: an interface controlcircuit 16; terminals 1 to 9; an output buffer 17; output impedanceadjusting circuits 18, 21 and 22; a timing adjusting circuit 19, adifferential output buffer 20; a band pass filter 23; an input buffer24; and a differential input buffer 25. The structure of the outputimpedance adjusting circuits 18, 21 and 22 is the same as that of theoutput impedance adjusting circuits 12, 13 and 14. The structure of thetiming adjusting circuit 19 is the same as that of the timing adjustingcircuit 10. The structure of the band pass filter 23 is the same as thatof the band pass filter 6.

[0057] The clock generated by the interface control circuit 16 issupplied, as the input clock CLKIN, to the terminal 1 through the outputbuffer 17 and the output impedance adjusting circuit 18. The clockgenerated by the interface control circuit 16 is input to the timingadjusting circuit 19 at the same time.

[0058] The timing adjusting circuit 19 receives the clock generated bythe interface control circuit 16, delays the clock (adjusts the timingof the clock) so that the relative phases of the data and the clock areoptimum on the receiving side, and outputs the timing-adjusted clocksignal to the differential output buffer 20.

[0059] The interface control circuit 16 outputs output data on thefalling edge (or the rising edge) of the clock that the circuit 16itself generates. The differential output buffer 20 receives the outputdata, latches the output data on the rising edge of the clock output bythe timing adjusting circuit 19, and outputs a complementary data pair(differential data). The differential output buffer 20 supplies thedifferential data, as differential input data DI+ and DI-, to theterminals 2 and 9 through the output impedance adjusting circuits 21 and22.

[0060] The output clock CLKOUT output from the semiconductor memory card1 to the terminal 5 is input to the interface control circuit 16 and thedifferential input buffer 25 through the band pass filter 23 and theinput buffer 24.

[0061] The differential output data DO+ and DO− output from thesemiconductor memory card 1 to the terminals 7 and 8 are input to thedifferential input buffer 25. The differential input buffer 25 senses,latches and outputs the output data DO which is the difference betweenthe differential output data DO+ and DO− on the rising edge of the clockoutput by the input buffer 24. The interface control circuit 16 latchesand receives the output data DO on the falling edge (or the rising edge)of the clock output by the input buffer 24.

[0062] As is apparent from FIG. 3, in the embodiment, only the hostapparatus 15 has a clock generating source. The semiconductor memorycard 1 synchronizes this one clock with the differential output data ofthe semiconductor memory card 1 by delaying the clock (adjusting thetiming) by the timing adjusting circuit 10 so that the clock and thedifferential output data are in an optimum phase relationship on thereceiving side, and outputs it as the output clock CLKOUT.

[0063]FIG. 4 will be described showing the waveforms of input and outputsignals of the semiconductor memory card 1 according to the firstembodiment and the timing relationship thereamong. In FIG. 4, thereference designations of the waveforms are the same as those shown inFIG. 1. As the waveforms of input signals, the waveforms of the inputclock CLKIN, the clock CLK, the differential input data DI+ and DI− andthe input data DI are shown. As the waveforms of output signals, thewaveforms of the output data DO, the clock CLK, the differential outputdata DO+ and DI, the timing-adjusted clock signal Delayed CLK and theoutput clock CLKOUT are shown.

[0064] The purpose of the adjustment by the timing adjusting circuits 10and 19 will be described with reference to the timing chart of FIG. 4.When the delay times of the clock and the data are different from eachother on the transmission line, on the receiving side, the phase of theclock is shifted from the appropriate timing where.the differential datais sensed and latched, so that the data cannot be correctly sensed orlatched on the receiving side. In particular, when the clock frequencyis increased and the data transmission cycle time is decreased, there isa possibility that the latch clock is input at a timing where thepotential difference between the non-inverted signal and the invertedsignal of the differential input data is not more than the sensingsensitivity. In such a case, the possibility is also high that amalfunction of data transmission occurs.

[0065] Therefore, in order that the timing between the input data DI+and DI− and the clock signal CLKIN is optimum in the semiconductormemory card 1, the host apparatus 15 adjusts the output timing of theinput data DI+ and DI− so that the differential input data DI+ and DI−and the clock signal CLKIN are synchronized with each other in anappropriate phase relationship on the receiving side (the semiconductormemory card 1). This enables the semiconductor memory card 1 toappropriately perform sensing and latching of the differential inputdata DI+ and DI−. That is, the host apparatus 15 supplies the input dataDI+ and DI− at a timing where the semiconductor memory card 1 can latchthe differential input data DI+ and DI− in a condition where thepotential difference between the data DI+ and DI− is not less than thesensing sensitivity and sufficiently large.

[0066] Likewise, for the signal output from the semiconductor memorycard 1, in order that the timing between the output data DO+ and DO− andthe clock CLKOUT is optimum in the host apparatus 15, the semiconductormemory card 1 adjusts the timing of the clock CLKOUT so that thedifferential output data DO+ and DO− and the clock CLKOUT aresynchronized with each other in an appropriate phase relationship on thereceiving side (the host apparatus 15). This enables the host apparatus15 to appropriately perform sensing and latching of the differentialoutput data DO+ and DO−.

[0067] It is necessary that the timing adjustment amount be fixed orvariable.

[0068] A structure where the delay circuit for timing adjustment isdisposed on the transmitting side and a structure where the delaycircuit is disposed on the receiving side can be considered. Moreover, astructure where the delay circuit for timing adjustment delays the dataand a structure where the delay circuit delays the clock may beconsidered. In the system (comprising the host apparatus and thesemiconductor memory card) of the embodiment, the timing adjustment isperformed on the transmitting side so that the relative phases of thedata and the clock are appropriate on the receiving side. The differencebetween the delay times of the data and the clock differs according tothe structures of the host apparatus and the semiconductor memory card.Generally, the difference between the delay times of the data and theclock depends on the structure of the transmitting side. The structureof the embodiment enables the receiving side to appropriately sense andlatch the data by using the input clock without adjusting the timingbetween the data and the clock. Consequently, compatibility can beensured when various kinds of host apparatuses and semiconductor memorycards are arbitrarily combined.

[0069] The clock output by the host apparatus is transmitted to thesemiconductor memory card without passing through any delay circuit. Theclock transmitted from the host apparatus and the semiconductor memorycard acts as a reference phase in the transmission system design. Forthe data and the clock transmitted from the host apparatus to thesemiconductor memory card, the host apparatus makes the relative phasesof the data and the clock appropriate on the receiving side (thesemiconductor memory card) by synchronizing the data and the clock witheach other by adjusting the output timing of the data.

[0070] The data output by the semiconductor memory card is transmittedto the host apparatus without passing through any delay circuit. For thedata and the clock transmitted from the semiconductor memory card to thehost apparatus, the semiconductor memory card synchronizes the clock andthe data with each other so that the relative phases of the clock andthe data are appropriate on the receiving side (the host apparatus), byadjusting the output timing of the clock. In particular, in asemiconductor memory card according to a second embodiment supportingthe prior art first and second operation modes and the operation mode(third operation mode) of the present invention, by the semiconductormemory card adjusting the output timing of not the data but the clock,the number of parts of the circuits switched in accordance with theoperation mode can be reduced.

[0071] <<Embodiment 2>>

[0072] The semiconductor memory card 601 and a host apparatus 615according to the second embodiment of the present invention will bedescribed with reference to FIG. 5 to FIG. 7 and FIG. 12. Thesemiconductor memory card 601 according to the second embodiment has aninterface circuit capable of operating with the operation mode switchedamong the high-speed operation mode shown in the first embodiment andthe prior art first and second operation modes. FIG. 5 is an explanatoryview showing the attributes and the functions of the terminals of thesemiconductor memory card 601 in each operation mode. FIG. 6 is aconcrete circuit diagram of the semiconductor memory card 601 switchableaccording to which of a plurality of operation modes is set. FIG. 7 is aflowchart of selection of the operation mode of the semiconductor memorycard 601 according to the second embodiment. The host apparatus 615according to the second embodiment to which the semiconductor memorycard 601 is attached operates in the first to the third operation modesby switching the internal connection. FIG. 12 is a concrete circuitdiagram of the host apparatus 615 according to the second embodiment ofthe present invention whose operation is switchable according to whichof the first to the third operation modes is set.

[0073] As shown in FIG. 5, in the semiconductor memory card 601,switching can be made among the card interface specifications (thenormal operation mode) of the prior art two operation modes (the firstand the second operation modes) shown in FIG. 9 and the interfacespecification (the high-speed operation mode, the third operation mode)of the first embodiment. The attributes and the functions of theterminals 1 to 9 in the third operation mode in FIG. 5 are the same asthose of the terminals 1 to 9 of the first embodiment. In other words,in the semiconductor memory card 601, when the third operation mode isselected, similar advantages to those of the semiconductor memory card 1of the first embodiment are obtained.

[0074] The semiconductor memory card 601 according to the secondembodiment has the circuit structure of FIG. 6, and the attributes andthe functions of the terminals are switched according to which of theoperation modes of FIG. 5 is set. The host apparatus 615 according tothe second embodiment has the circuit structure of FIG. 12, and theattributes and the functions of the terminals are switched according towhich of the operation modes of FIG. 5 is set. FIG. 6 shows input andoutput circuits between the terminals 1, 2, 5 and 7 to 9 and theinterface control circuit 4 a. FIG. 12 shows input and output circuitsof the terminals 1, 2, 5 and 7 to 9. The attributes and the functions ofthe terminals 3, 4 and 6 acting as power supply terminals do not changeirrespective of which of the first to the third operation modes is set.In FIG. 6 and FIG. 12, the terminals 3, 4 and 6 are not shown.

[0075] In FIG. 6 and FIG. 12, elements the same as those of the firstembodiment are designated by the same reference numerals. The interfacecontrol circuit 4 a has input and output terminal parts 401 to 421 toand from which signals are input and output from and to circuitelements. In FIG. 6, reference numeral 26 represents a three-stateoutput buffer, and reference numeral 27 represents an input buffer. Adelay amount selecting part 28 selects and decides the timing delayamount of the timing adjusting circuit 10. A passband selecting part 29selects and decides the passband of the band pass filter 6. Thesemiconductor memory card 601 has switching circuits SW1 to SW7, andswitches the condition of connection between the terminals 1 to 9 andthe interface control circuit 4 a by controlling the switching circuits.By doing this, the semiconductor memory card 601 switches among theconditions of the first, the second and the third operation modes.Resistors R1, R2 and R3 constitute the above-mentioned output impedanceadjusting circuits 14, 13 and 12, respectively.

[0076] The interface control circuit 4 a writes the selected value ofthe delay time into an internal register in accordance with the clockfrequency. The interface control circuit 4 a outputs from the terminalpart 410 an output signal DELAY_ADJUST read from the internal register,and writes it into the delay amount selecting part 28. The timingadjusting circuit 10 delays the clock by a delay time corresponding tothe value of the output signal DELAY_ADJUST output by the delay amountselecting part 28 (the third operation mode).

[0077] The interface control circuit 4 a writes the median value of thepassband and the selected value of the bandwidth of the band pass filter6 into the internal register in accordance with the clock frequency. Theinterface control circuit 4 a outputs from the terminal part 411 anoutput signal BAND_SELECT read from the internal register, and writes itinto the passband selecting part 29. The band pass filter 6 allows theclock input from the terminal 1 to pass therethrough with the medianvalue of the frequency and the bandwidth corresponding to the outputsignal BAND_SELECT output from the passband selecting part 29 (the thirdoperation mode).

[0078] The switching circuits SW1 to SW7 are all switched to the side of1 or 0 in accordance with whether the value of the control signal is 1or 0. By the switching circuits SW1 to SW7 being switched to the side of1, the circuit structure becomes the one shown in FIG. 1. That is, theoperation mode is switched to the third operation mode for high-speeddata transmission. By the switching circuits SW1 to SW7 being switchedto the side of 0, the semiconductor memory card 1 operates in the firstor the second operation mode. In the second operation mode, thethree-state output buffer 26 connected to the terminals 1, 2, 8 and 9 isset in a high-impedance condition, and in the first operation mode, thethree-state output buffer 26 connected to the terminals 1, 2, 8 and 9 isswitched between an output condition and the high-impedance condition. Amode switching signal MODE output by the output terminal part 401controls the switching of the switching circuits SW1 to SW7.

[0079] When the semiconductor memory card 601 is attached to the hostapparatus 615 or when power supply is started with the semiconductormemory card 601 attached to the host apparatus 615 (when thesemiconductor memory card 601 is activated), the semiconductor memorycard 601 initializes the mode switching signal MODE to 0 (the firstoperation mode). When the semiconductor memory card 601 is activated,the host apparatus 615 inputs to the semiconductor memory card 601command data for setting the operation mode of the semiconductor memorycard 601. The interface control circuit 4 a sets the operation modeselected in accordance with the command data to a mode setting part ofan internal first resister. The mode switching signal MODE correspondingto the set operation mode is output from the output terminal part 401.For example, when the set operation mode is the third operation mode,the switching circuits SW1 to SW7 initialized to the side of 0 areswitched to the side of 1 in accordance with the command data from thehost apparatus 615. Input and output of the output terminal part 405,the input terminal part 409 and the input terminal part 418 of the inputand output terminals 401 to 421 of the interface control circuit 4 aeffectively work.

[0080] Under a condition where the switching circuits SW1 to SW7 areswitched to the side of 0, the semiconductor memory card 601 accordingto the second embodiment operates as follows: The terminal parts 402 to404 of the interface control circuit 4 a performs data input and outputthrough the terminal 8. The terminal part 403 outputs to the three-stateoutput buffer 26 a control signal to permit or inhibit output. When aninput data that is input from the terminal 8 through the input buffer 27is present, the three-state output buffer 26 is inhibited fromoutputting data. This prevents a collision between the data output bythe three-state output buffer 26 and the input data. Likewise, the inputand output terminal parts 406 to 408 perform data input and outputthrough the terminal 7. The input and output terminal parts 419 to 421perform data input and output through the terminal 9. The input andoutput terminal parts 412 to 414 perform data input and output throughthe terminal 1. The input and output terminal parts 415 to 417 performcommand input and response input through the terminal 2.

[0081] In FIG. 12, the host apparatus 615 comprises: switching circuits616 to 621; three-state output buffers 622, 624, 627, 629 and 631;buffers 17, 24, 623, 625, 626, 628, 630 and 632; a band pass filter 23;a timing adjusting circuit 19; a passband selecting part 633; a delayamount selecting part 634; and resistors R4 to R6. The host apparatus615 and the semiconductor memory card 601 perform synchronous datatransmission according to a master/slave method with the host apparatus615 as the master and the semiconductor memory card 601 as the slave.The switching circuits 616 to 621 are switched to the side of 1 or 0 inaccordance with whether the value of the control signal output from aterminal part 1601 of the interface control circuit 16 is 1 or 0. In thefirst and the second ope ration modes, the switching circuits 616 to 621are switched to the side of 0. In the third operation mode, theswitching circuits 616 to 621 are switched to the side of 1. In thethird operation mode, the circuit structure and the operation of thehost apparatus 615 are the same of those of the host apparatus of thefirst embodiment. The resistors R4, R5 and R6 are implementation of theoutput impedance adjusting circuits 18, 21 and 22 of FIG. 3. Thepassband selecting part 633 decides the median value of the frequencyand the bandwidth of the band pass filter 23 in accordance with theoutput signal output from a terminal part 1610 of the interface controlcircuit 16. The delay amount selecting part 634 decides the delay timeof the clock at the timing adjusting circuit 19 in accordance with theoutput signal output from a terminal part 1616 of the interface controlcircuit 16. In the first operation mode, the three-state buffer 624 andthe buffer 625 bidirectionally transmit and receive data through theterminal 7. In the second operation mode, the three-state buffer 624 isset in a high-impedance condition. The host apparatus 615 receives datathrough the terminal 7. In the first and the second operation modes, theother pairs of three-state buffers and buffers bidirectionally transmitand receive data, output data or do not operate according to thespecification of FIG. 5.

[0082] Next, a method of selecting a mode among the three operationmodes in the semiconductor memory card 601 will be describedwithreference to the flow chart shown in FIG. 7. FIG. 7 shows the procedureby which the host apparatus 615 initializes the semiconductor memorycard 601. In the initial condition (when the semiconductor memory card601 is activated), the semiconductor memory card 601 is set so as tooperate in the first operation mode.

[0083] First, the host apparatus 615 supplies power to the semiconductormemory card 601 (step S1). The host apparatus 615 and the semiconductormemory card 601 are initialized to the first operation mode. At step S2,a microcomputer provided in the host apparatus 615 waits for input of anoperation mode setting instruction (step S2). When an operation modesetting instruction is input, the process proceeds to step S3, and whenno operation mode setting instruction is input, step S2 is repeated.When an operation mode setting instruction is input, it is determinedwhether the set operation mode is the first operation mode or not (stepS3). When the set operation mode is the first operation mode, theprocess proceeds to step S4, and when the set operation mode is not thefirst operation mode, the process proceeds to step S6.

[0084] At step S4, the card interface control circuit 16 of the hostapparatus 615 outputs an initialization command of the first operationmode to the semiconductor memory card 601. The host apparatus 615 andthe semiconductor memory card 601 operate according to the interfacespecification of the first operation mode (step S5).

[0085] At step S6, the card interface control circuit 16 of the hostapparatus 615 outputs an initialization command of the second operationmode to the semiconductor memory card 601. The host apparatus 615 andthe semiconductor memory card 601 operate according to the interfacespecification of the second operation mode (step S7). At step S8, thecard interface control circuit 16 reads operation mode information setin a register in the semiconductor memory card 601. At step S9, the cardinterface control circuit 16 determines whether the read operation modeinformation includes an effective bit of the third operation mode ornot. When an effective bit of the third operation mode is not included,the process proceeds to step S10, and the host apparatus 615 and thesemiconductor memory card 601 continue to operate according to theinterface specification of the second operation mode.

[0086] When it is determined at step S9 that an effective bit of thethird operation mode is included, the process proceeds to step S11. Thecard interface control circuit 16 of the host apparatus 615 outputs tothe semiconductor memory card 601 a command for switching to the thirdoperation mode. The card interface control circuit 16 instructs thepassband selecting part 633 to set the median value of the frequency andthe band width of the band pass filter 23 to values suitable for thethird operation mode, and instructs the delay amount selecting part 634to set the delay time of the clock at the timing adjusting circuit 19 toa value suitable for the third operation mode (step S11).

[0087] Then, at step S12, the process waits until a predetermined timeelapses. The predetermined time is set to a time sufficient for thesemiconductor memory card 601 having received the command for switchingto the third operation mode, to perform internal setting according tothe third operation mode. After the predetermined time has elapsed, thehost apparatus 615 and the semiconductor memory card 601 operateaccording to the interface specification of the third operation mode(step S13).

[0088] As described above, according to the present invention, inputdata and output data never collide on the data line, and this enableshigh-speed data communication control. Moreover, by adoptingdifferential data input and output circuits (complementary datatransmission), the S/N ratio of the reception data is improved. Thisenables the-receiving side to sense the reception data at high speed.The improvement of the S/N ratio enables the amplitude of thetransmission data to be small on the transmitting side. By the dataamplitude being small, the clock frequency can be increased without theslew rate in the output stage being improved. Complementary datatransmission was adopted only in asynchronous data communication inprior arts, and the idea of adopting complementary data transmission insynchronous data transmission was absent.

[0089] In the present invention, an input clock and an output clockhaving different phases are separately generated, and the data and theclock are transmitted in synchronism with each other so that the clockand the data have optimum relative phases on the receiving side.According to the present invention, an advantageous effect is obtainedthat the timing shift between the data and the clock due to a delay onthe transmission line is never caused. In synchronous data communicationaccording to the prior art master/slave method, the clock wastransmitted only from the master apparatus (host apparatus) to the slaveapparatus (semiconductor memory card), and the idea of transmittinganother clock from the slave apparatus to the master apparatus wasabsent.

[0090] The semiconductor memory card timing-adjusts the input clockoutput by the host apparatus, and transmits the timing-adjusted clockand the data in synchronism with each other so that they are in anoptimum phase relationship on the receiving side (host apparatus).According to the present invention, an effect is obtained that asemiconductor memory card not requiring a clock generating part isrealized. In synchronous data communication according to themaster/slave method, it is difficult for the master apparatus toappropriately control the entire communication unless the masterapparatus outputs a clock. In the prior art, the master apparatus input,by using the lock which the master apparatus itself outputs, the datathat the slave apparatus output by using the clock which the masterapparatus output and the slave apparatus received. However, since thesignal transmission path of the data transmitted from the slaveapparatus (the clock with which data has been transmitted goes and thedata returns between the master apparatus and the slave apparatus) andthat of the clock generated by the master apparatus are completelydifferent from each other, the phase relationship therebetween isshifted at a particularly high data rate. Although it is unnecessary totransmit and receive a clock in asynchronous data transmission in whichno clock is transmitted, generally speaking, the data rate is lower inasynchronous data transmission than in synchronous data transmission.The present invention relates to an apparatus and a method forperforming synchronous data communication according to the master/slavemethod in which only the master apparatus (host apparatus) generates aclock. The master apparatus transmits a clock for data transmission fromthe master apparatus to the slave apparatus (semiconductor memory card).The slave apparatus uses the clock or a clock obtained by delaying theclock as a clock for data transmission from the slave apparatus to themaster apparatus, and transmits the clock to the master apparatustogether with the data. In the data transmission from the slaveapparatus to the master apparatus, a large phase shift is not causedbecause the data and the clock are transmitted substantially on the samepath. By the timing adjusting circuit of the slave apparatus adjustingthe phase of the clock, the data and the clock are in an appropriatephase relationship in the master apparatus on the receiving side. Thepresent invention realizes a slave apparatus (semiconductor memory card)performing high-data-rate and stable data transmission according to themaster/slave method under a condition where the master apparatus (hostapparatus) maintains a function to appropriately control the entirecommunication.

[0091] <<Embodiment 3>>

[0092] The interface apparatus for the semiconductor memory cardaccording to the third embodiment of the present invention (hereinafter,will be referred to as “interface apparatus”) will be described withreference to FIG. 13. FIG. 13 is a block diagram of a system having ahost apparatus 615, an interface apparatus 1301 according to the thirdembodiment and a semiconductor memory card 1302 according to the thirdembodiment.

[0093] In FIG. 13, the host apparatus 615 is the same as the hostapparatus according to the second embodiment.

[0094] The interface apparatus 1301 has a connection terminal to thehost apparatus 615 and the interface circuit (FIG. 6) which are the sameas those of the semiconductor memory card 601 according to the secondembodiment. The interface apparatus 1301 is an interface adaptor havingapproximately the same external shape with that of the semiconductormemory card 601 according to the second embodiment. The semiconductormemory card 1302 is smaller in size than the semiconductor memory card601 according to the second embodiment and has no interface circuit. Theinterface apparatus 1301 has terminals for connecting to thesemiconductor memory card 1302 and an attachment device for thesemiconductor memory card 1302.

[0095] The interface apparatus 1301 carrying the semiconductor memorycard 1302 is capable of being attached to the host apparatus 615 (thesecond embodiment) to which the semiconductor memory card 601 of thesecond embodiment can be attached. The interface apparatus 1301 carryingthe semiconductor memory card 1302 has mechanical and electricalcompatibility with the semiconductor memory card 601 according to thesecond embodiment.

[0096] The semiconductor memory card 1302 has the configuration of thesemiconductor memory card 601 according to the second embodiment fromwhich the interface circuit is subtracted. The semiconductor memory card1302 has a data storing portion 2 and a writing and reading controlcircuit 3 which are the same as those of the semiconductor memory card601 according to the second embodiment.

[0097] The system according to the third embodiment having the hostapparatus 615, the interface apparatus 1301 and the semiconductor memorycard 1302 performs the same operation and has the same effect as thoseof the system according to the second embodiment having the hostapparatus 615 and the semiconductor memory card 601.

[0098] The interface apparatus according to-the third embodiment had theinterface circuit of the semiconductor memory card 601 according to thesecond embodiment. In place of this, the interface apparatus for thesemiconductor memory card may have the interface circuit of thesemiconductor memory card 1 according to the first embodiment. Thisinterface apparatus is capable of operating by attaching and connectingto the host apparatus according to the first embodiment.

[0099] The host apparatus, the semiconductor memory card and theinterface apparatus for semiconductor memory card according to thepresent invention are adaptable to the interface specifications of aplurality of operation modes, and particularly, are adaptable to thehigh-speed operation mode without the number of connection terminalsbeing increased. The host apparatus, the semiconductor memory card andthe interface apparatus for semiconductor memory card according to thepresent invention execute the control method of performing communicationaccording to the interface specification of the present invention by aprocedure through operation modes of the prior art semiconductor memorycard. Consequently, the terminal structure of the semiconductor memorycard according to the present invention maintains compatibility withthat of the prior art semiconductor memory card, and a high datatransfer rate can be realized between the semiconductor memory card andthe host apparatus according to the present invention.

[0100] The host apparatus, the semiconductor memory card and theinterface apparatus for semiconductor memory card according to thepresent invention are adaptable to the interface specifications of aplurality of operation modes by switching the switches according towhich of the operation modes is set, and particularly, are adaptable tothe high-speed operation mode with a simple structure without the numberof terminals being increased. Moreover, impedance matching with thesignal lines can be obtained. By the band pass filter, a clock of apredetermined frequency band can be captured with reliability. Byoptimally setting the frequency of the band pass filter, a timing shiftdue to a reflected wave can be prevented.

[0101] Although the invention has been described in its preferred formwith a certain degree of particularity, it is understood that thepresent disclosure of the preferred form has been changed in the detailsof construction and the combination and arrangement of parts may beresorted to without departing from the scope and the spirit of theinvention as hereinafter claimed.

1. A semiconductor memory card comprising: a data storing part; acontrol part writing and reading data into and from said data storingpart; an interface circuit; and a plurality of input and outputterminals, wherein in said input and output terminals, roles of a datainput terminal pair and a data output terminal pair are each allotted toa different terminal pair so that no terminal pair acts as both the datainput terminal pair and the data output terminal pair, and a clock inputterminal and a clock output terminal are included, and said interfacecircuit receives an input clock from said clock input terminal, receivesa complementary input data pair synchronized with said input clock fromsaid data input terminal pair, outputs a complementary output data pairfrom said data output terminal pair, and outputs an output clocksynchronized with said complementary output data pair from said clockoutput terminal.
 2. A semiconductor memory card in accordance with claim1, wherein said semiconductor memory card performs data input and outputwith a host apparatus, said interface circuit receives an input clockoutput by said host apparatus and input data synchronized with saidinput clock, and said interface circuit generates said output clockhaving a phase different from a phase of said input clock and beingsynchronized with said complementary output data pair by adjusting atiming of said input clock, outputs said output clock from said clockoutput terminal, and outputs said complementary output data pair fromsaid data output terminal pair.
 2. A semiconductor memory cardcomprising: an interface circuit setting an attribute and a function ofeach of a plurality of input and output terminals and performinginternal setting in accordance with an operation mode selected and setfrom among a plurality of operation modes including a high-speedoperation mode; and said plurality of input and output terminals,wherein in said high-speed operation mode, said plurality of input andoutput terminals comprise: a clock input terminal to which an inputclock is input; a clock output terminal from which an output clock isoutput; a data input terminal pair to which a complementary input datapair synchronized with said input clock is input; and a data outputterminal pair from which a complementary output data pair is output, andsaid interface circuit comprises the following as elements operating atleast in said high-speed operation mode: a switch capable of beingswitched in accordance with said high-speed operation mode; adifferential input buffer receiving said complementary input data pair,sensing a difference between said complementary input data pair by saidinput clock, and latching said difference; a differential output bufferreceiving output data and outputting said output data by said inputclock as said complementary output data pair; and a timing adjustingcircuit receiving said input clock, adjusting a timing of said inputclock with said complementary output data pair, and outputting, as saidoutput clock, said input clock timing-adjusted so as to be synchronizedwith said complementary output data pair.
 4. A semiconductor memory cardin accordance with claim 3, wherein said interface circuit has outputimpedance adjusting circuit(s) each of between said data output terminalpair and said differential output buffer and between said output clockterminal and said timing adjusting circuit.
 5. A semiconductor memorycard in accordance with claim 3 or 4, wherein said interface circuitfurther comprises a band pass filter receiving said input clock andallowing only a predetermined frequency band component to pass throughsaid band pass filter.
 6. A semiconductor memory card in accordance withclaim 5, wherein a passband frequency of said band pass filter isselectable.
 7. A method of controlling, in a high-speed operation mode,a semiconductor memory card having a plurality of input and outputterminals and performing data input and output with a host apparatus ina plurality of operation modes including a normal operation mode andsaid high-speed operation mode, said method comprising the steps of:setting said high-speed operation mode in response to a setting commandof said high-speed operation mode from said host apparatus; switching anoperation of said semiconductor memory card so that data transmissionand reception can be performed in said high-speed operation mode;allotting roles of a data input terminal pair, a data output terminalpair, a clock input terminal and a clock output terminal separately tosaid input and output terminals so that none of said input and outputterminals has a plurality of roles; inputting an input clock from saidclock input terminal and inputting a complementary input data pairsynchronized with said input clock from said data input terminal pair;generating an output clock having a phase different from a phase of saidinput clock, by adjusting a timing of said input clock; and outputtingsaid output clock from said clock output terminal and outputting acomplementary output data pair synchronized with said output clock fromsaid data output terminal pair.
 8. A slave apparatus performingsynchronous data transmission according to a master/slave method with ahost apparatus as a master and a slave apparatus as a slave, said slaveapparatus comprising: an input part inputting a clock and data output bysaid host apparatus in synchronism with each other; and an output partoutputting to said host apparatus said clock being input or a clockobtained by timing-adjusting said clock, and data in synchronism witheach other.
 9. A slave apparatus in accordance with claim 8, whereinsaid slave apparatus is a semiconductor memory card.
 10. An interfaceapparatus for a semiconductor memory card comprising: an interfacecircuit setting an attribute and a function of each of a plurality ofinput and output terminals and performing internal setting in accordancewith an operation mode selected and set from among a plurality ofoperation modes including a high-speed operation mode; and saidplurality of input and output terminals, wherein in said high-speedoperation mode, said plurality of input and output terminals comprise: aclock input terminal to which an input clock is input; a clock outputterminal from which an output clock is output; a data input terminalpair to which a complementary input data pair synchronized with saidinput clock is input; and a data output terminal pair from which acomplementary output data pair is output, and said interface circuitcomprises the following as elements operating at least in saidhigh-speed operation mode: a switch capable of being switched inaccordance with said high-speed operation mode; a differential inputbuffer receiving said complementary input data pair, sensing adifference between said complementary input data pair by said inputclock, and latching said difference; a differential output bufferreceiving output data and outputting said output data by said inputclock as said complementary output data pair; and a timing adjustingcircuit receiving said input clock, adjusting a timing of said inputclock with said complementary output data pair, and outputting, as saidoutput clock, said input clock timing-adjusted so as to be synchronizedwith said complementary output data pair.